Consider the following processors (ns stands for nanoseconds). MAR ← X In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Consider evaluating the following expression tree on a machine with load-store architecture in which memory can be accessed only through load and store instructions. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode(IF), (2) Operand Fetch (OF), (3) Perform Operation(PO) and (4) Write back the result (WB). Generally, we tend to think computer organization and computer architecture as same but there is slight difference. The number of rows of memory cells in the DRAM chip is 2, The size of the physical address space of a processor is 2. I. L1 must be a write-through cache The subject includes Machine instructions and addressing modes, ALU, Data‐path, and control unit, Instruction pipelining, Memory hierarchy: cache, Main memory, Secondary storage, and I/O interface (Interrupt and DMA mode) with a weightage of 6-9 marks. The IF, ID and WB stages take one clock cycle each to complete the operation. What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation'? The test contains all the questions related to Computer Organization and Architecture. Control hazard penalties can be eliminated by dynamic branch prediction, The use of multiple register windows with overlap causes a reduction in the number of memory accesses for, I. The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is, The following code segment is executed on a processor which allows only register operands in its instructions. What is the time taken for this transfer? f = c + e Get the notes of all important topics of Computer Organization & Architecture subject. Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The first tage(with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. These notes will be helpful in preparing for semester exams and competitive exams like GATE, NET and PSU's. Compulsory misses occur due to first time access to the block. e = b + f The list ratio for read access is only 80%. Assuming that all operations take their operands from registers, what is the minimum number of registers needed to execute this program without spilling? Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. In the instruction shown, the first register stores the result of the operation performed on the second and the third registers. Get the study material and tips for upcoming GATE, BARC, ISRO, and other CS exams. The number of bits for the TAG field is _____. I1: ADD R1, R2, R3 The stack pointer(SP) points to the top element of the stack. Initialize the address register The instructi ons produce result only in a register. An access sequence of cache block addresses is of length N and contains n unique block addresses.The number of unique block addresses between two consecutive acceses to the same block address is bounded above by k. What is the miss ratio if the access sequence is passed through a cache of  associativity A ≥ k exercising least-recently-used replacement policy? The throughput increase of the pipeline is___________ percent. 17 Free videos ₹3,500.00. After the execution of this program, the content of memory location 2010 is: Assume that the memory is byte addressable and the word size is 32 bits. When two 8-bit  number A7....A0  and  B7 ..... B0  in 2's  complement representation (with A0 and B0 as the least significant bits) are added using ripple-carry adder, the sum bits obtained are S7.....S0 and the  carry bits are C7....C0 . COMPUTER ORGANIZATION Logic Gates, Boolean Algebra, Combinational Circuits 2. Also, Output of a 4 bit multiplier is 8 bits. Computer Architecture and Organisation Q No: 48 The access time of cache memory is 15 ns and main memory is 100 ns. The miss rate L2 expressed correct to two decimal places is _________. The amount of ROM needed to implement a 4 bit multiplier is, Register renaming is done in pipelined processors. Assume that the caches use the referred-word-first read policy and the write back policy. We have also provided number of questions asked since 2007 and average weightage for each subject. c = a + b; Consider a RISC machine where each instruction is exactly 4 bytes long. Consider a hypothetical processor with an instruction of type LW R1 , 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. Assume that the data cache is initially empty. The following code is to run on a pipelined processor with one branch delay slot: Cache memory is located on the path between the processor and the … Binary logic deals with binary variables and with operations that assume a logical meaning. What is the total time taken for these transfers? A cache memory unit with capacity of N words and block size of B words is to be designed. The memory is byte addressable. Assume that under identicalv conditions, for the same input, a program running on p2 takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on p2. It is used to describe, in algebraic or tabular form, the manipulation done by logic circuits called gates.Gates are Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. PC ← Y III. The pipeline registers are required between each stage and at the end of the last stage.Delays for the stages and for the pipeline registers are as given in the figure. GATE Computer science and engineering subject Computer Organization and Architecture (Common Bus System) from morris mano for computer science and information technology students doing B.E, B.Tech, M.Tech, GATE exam, Ph.D. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. The cache hit-ratio is 0.9. The binary operators used in this expression tree can be evaluated by the machine only when the operands are in registers.     d = d * d; Logic Gates | Computer Organization and Architecture Tutorial with introduction, evolution of computing devices, functional units of digital system, basic operational concepts, computer organization and design, store program control concept, von-neumann model, parallel processing, computer registers, control unit, … I5: MUL R7, R8, R9, S1:There is an anti-dependence between instruction I2 and I5 If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits. GATE 2019 CSE syllabus contains Engineering mathematics, Digital Logic, Computer Organization and Architecture, Programming and Data Structures, Algorithms, Theory of Computation, Compiler Design, Operating System, Databases, Computer Networks, General Aptitude. The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns. The number of clock cycles for the EX stage depends on the instruction. e = c + a; An exception cannot be allowed to occur during execution of an RFE instruction, For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary? In addition, the tutor has solved a number of GATE problems related to Computer Organization to reinforce the concepts. We have also provided number of questions asked since 2007 and average weightage for each subject. Consider a 4 stage pipeline processor. Audience. Memory ← MBR The size of the tag filed in bites is __________.                                 SUB R8, R7, R4. The cache hit ratio for this initialization loop is, Delayed branching can help in the handling of control hazards, For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false. 25 –26 27 Binary Adder –32 Arithmetic Logic Unit (ALU) 32 –35 36 Assignment 1 Computer Organization and Architecture Quiz Start online test with daily Computer Organization and Architecture quiz for Gate computer science engineering exam 2019-20. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is __________$\times$ 106 bytes/sec. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is ______________________. OP Ri, Rj, Rk A processor has 40 distinct instructions and 24 general purpose registers. Consider the following instruction sequence. I. The miss penalty from the L2 cache to main memory is 18 clock cycles. 18 Free videos ₹4,500.00. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipelined delay, the clock speed is reduced to 2 gigahertz. Do not apply any optimization other than optimizing register allocation. 1 Modified bit A CPU generally handles an interrupt by executing an interrupt service routine. Assume that the dirty bit is always 0 for all the blocks in the caches. (B) represents organization of single computer containing a control unit, processor unit and a memory unit. A 32-bit instruction word has an opcode, two register operands and an immediate operand. Computer Organization and Architecture Tutorial provides in-depth knowledge of internal working, structuring, and implementation of a computer system. The time to perform addition using this adder is. The number of conflict misses experinced by the cache is ____________ . Consider a machine with a byte addressable main memory of 216 bytes. The CPU generates a 20-bit address of a word in main memory. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. The lines of a set are placed in sequence one after another. The cache block size is 8 words and the word size is 4 bytes. I4 : STORE Memory [R4] ← R1 The size of the data count register of a DMA controller is 16 bits. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. Ideal way to study CAO would be to go through syllabus and recommended books then solving previous year questions and questions at the end of the chapter in the book. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache? A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. I1 : ADD R2 ← R7 + R8 In execution of a program, 60% of memory read are for instruction fetch and 40% are for memory operand fetch. Computer Networks. What is the number of clock cycles taken to complete the following sequence of instructions? Further the Offset is always with respect to the address of the next instruction in the program sequence. The time required to perform one refresh operation on all the cells in the memory unit is. What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? As many bits as the minimum needed to identify the memory block mapped in the cache. The program below uses six temporary variables a, b, c, d, e, f. a = 1 The complete array is accessed twice. 2. In the above sequence, R0 to R8 are general purpose registers. The read access time of main memory is 90 nanoseconds. Computer Organization MCQ for GATE This computer organization mcq based tutorial provides some practice questions for GATE CS/IT Exam.Computer organization and architecture is an important subject for GATE CSE Exam. In Computer Science Engineering (CSE), Computer Organization and Architecture is a set of rules that describe the capabilities and programming model of a computer. Which one of the following memory block will NOT be in cache if LRU replacement policy is used? Computer system architecture by M. Morris Mano.Computer architecture by Briggs. Which of the following array elements has the same cache index as ARR [0] [0]? The representation of X in hexadecimal notation is, Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. A certain processor uses a fully associative cache of size 16 kB. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. GATE Computer science and engineering subject Computer Organization and Architecture (Match Logic) from morris mano for computer science and information technology students doing B.E, B.Tech, M.Tech, GATE exam, Ph.D. Consider the following processor design characteristics. This Test will cover complete Computer Organization and Architecture with very important questions, starting off from basics to advanced level. Which of the following lines of the data cache will be replaced by new blocks in accessing the array for the second time? ID: Instruction Decode and Operand Fetch for (j = 0; j < 1024; j ++) COMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational Circuits 1. ARR [i] [j] = 0.0; What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?      If count != 0 go to LOOP. If the clock frequency of p1 is 1GHz, then the clock frequency of p2 (in GHz) is _________. Best Books for Computer Organization and Architecture, GATE Weightage Analysis for Computer Organization, Computer Organization and Architecture Important Formulas, Notes on Machine Instructions and Addressing Modes, AAI ATC Recruitment Notification 2020 for Junior Executive (JE) ATC, AO & Technical, AFCAT 1 2021 Notification Out: Check Vacancies, Apply Online Link, Fee & Eligibility, NIELIT Scientist B & Technical Assistant A Answer Key 2020: Download, Key Challenge, PSU Recruitment through GATE 2021 - Jobs in PSU through GATE Score, Machine Instructions and Addressing Modes. The L2 cache must be at least as large as the L1 cache, Which of the following are NOT true in a pipelined processor? If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. TOC & Compiler Design. Assume that the memory system has 16 address lines denoted by A15 to A0. Consider a machine with a byte addreassable main memory of $ 2^{32} $ bytes divided into blocks of size 32 bytes. b = c + e Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory? Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. GATE Computer Science and IT Syllabus - Section A: Engineering Mathematics ... Computer Organization and Architecture: Section D: Programming and Data Structures: Section E: Algorithms: Section F: Theory of Computation: Section G: Compiler Design: Section H: Operating System: Section I: Databases: Consider a 2-way set associative cache with 256 blocks and uses LRU replacement, Initially the cache is empty. GATE CS Topic wise Questions Computer Organization and Architecture www.gatehelp.com YEAR 2001 Question.                                 ADD R7, R5, R6 Filed Under: CO & Architecture, Subjects Tagged With: computer architecture, computer organization, gate-material, gatecse discussion Primary Sidebar Search this website S3:Within an instruction pipeline an anti-dependence always creates one or more stalls. The size of double is 8Bytes. The minimum average latency (MAL) is _____. I3 : ADD R1 ← R2 + R3 Consider a machine with a byte addressable main memory of 220 bytes, block size of 16 bytes and a direct mapped cache having 212 cache lines. The speed up achieved in this pipelined processor is _____. MBR ← PC A processor can support a maximum memory of 4GB, where the memory is word-addressable (a word consists of two bytes). The width of the physical address on a machine is 40 bits. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. II. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. GATE 2019 CSE syllabus contains Engineering mathematics, Digital Logic, Computer Organization and Architecture, Programming and Data Structures, Algorithms, Theory of Computation, Compiler Design, Operating System, Databases, Computer Networks, General Aptitude. It consist of approx 8-10 marks questions every year in GATE Exam. These video classes have been developed based on the latest GATE syllabus and will be useful for undergraduate students of Computer Science and Information Technology as well as those preparing for GATE exams. The only data memory references made by the program are those to array ARR, The total size of the tags in the cache directory is. The amount of increment depends on the size of the data item accessed, Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? A certain processor deploys a single-level cache. The block size in L2 cache is 16 words. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________. The number of bits available for the immediate operand field is __________. I3: SUB R4, R1, R5 III. The following sequence of accesse to memory blocks, (0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129). It is useful in creating self-relocating code LOOP:Load a byte from device So, what I would suggest is : 1. Instruction fetches, In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is, Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation What is the number of clock cycles needed to execute the following sequence of instructions? S2:There is an anti-dependence between instructions I2 and I4 c = 20 }. 2020 © GATE-Exam.in | Complete Solution for GATE, Computer Science and Information Technology, Machine instructions and addressing modes, Memory Hierarchy: Cache, Main Memory and Secondary Storage, Load the starting address of the subroutine in. The time taken for a single refresh operation is 100 nanoseconds. The processor sends 32 bit addresses to the cache controller. Which one of above statements is/are correct? I2: MUL R7., R1, R3 After execution of the CALL instruction, the value of the stack pointer is. The current value of SP is (016E)16. Conflict misses are those misses which occur due to contention of multiple blocks for the same cache set. Instruction … Consider two processors p1 and p2 executing the same instruction set. Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2.      Initialize the count to 500 It must be a trap instruction A main memory unit with a capacity of 4 megabytes is built using 1M×1-bit DRAM chips.Each DRAM chip has 1K rows of cells with 1K cells in each row. The following section contains various questions … L2 must be a write-through cache Instruction I4 is the only branch instruction and its branch target is I9. d = a + b d = c * a; 512 bytes of data are stored in a bit serial manner in a sector. The new design has a total of eight pipeline stages. If no intermediate results can be stored in memory, what is the minimum number of registers needed to evaluate this expression? The size of the address bus of the processor is at least bits. Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________. Where operation Op is performed on contents of registers Rj and Rk and the result is stored in register Ri. Register saves and restores Thus, the 0th sector is addressed as 〈0,0,0〉, the 1st sector as 〈0,0,1〉, and so on. How many data cache misses will occur in total? When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. 1. It has 64 registers, each of which is 32 bits long. The processor needs to transfer a file of 29, 154 kilobytes from disk to main memory. The content of each of the memory locations from 2000 to 2010 is 100. Each of these instructions has the following format. A hard disk has 63 sectors per track, 10 platters each with 2 recording surfaces and 1000 cylinders. The word length is 32 bits. The number of memory references for accessing the data in executing the program completely is: Assume that the memory is word addressable. Conditional and unconditional branch instruction use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Assume that there are no stalls in the pipeline. I4: ADD R3, R2, R4 MUL R5, R0, R1 The IF, OF and WB stages take 1 clock cycle each for any instruction. PDF | On Nov 26, 2018, Firoz Mahmud published Lecture Notes on Computer Architecture | Find, read and cite all the research you need on ResearchGate (A) refers to a computer system capable of processing several programs at the same time. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns. To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. The associativity of L2 must be greater than that of L1 This is not the official website of GATE. The pipelined processor uses operand forwarding from the PO stage to the OF stage. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns. Assume that all variables are dead after this code segment. for (i = 0; i < 1024; i ++) Register renaming can eliminate all register carried WAR hazards All instructions other than the branch instruction have an average CPI of one in both the designs. Machine Instructions. Computer Organization & Architecture Notes, GATE Computer Science Notes, GATE Topic Wise Notes, Ankur Gupta GATE Notes, GATE Handwritten Notes, Topper Notes Consider the following program segment. For computer based on three-address instruction formats, each address feild can be used to specify which of the following: Improve your score by attempting Computer Organization and Architecture objective type MCQ questions listed along with detailed answers. 1 Valid bit Which of the instructions   I1,  I 2, I3 or  I4 can legitimatel y occupy the delay slot without any other program modification? It is our sincere effort to help you. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack? III. The address of a sector is given as a triple 〈c,h,s〉, where c is the cylinder number, h is the surface number and s is the sector number. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The number of bits in the TAG, LINE and WORD fields are respectively: Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. https://gradeup.co/.../computer-organization-and-architecture Computer Organization and Architecture: Machine instructions and addressing modes, ALU and data-path, CPU control design, Memory interface, I/O interface (Interrupt and DMA mode), Instruction pipelining, Cache and main memory, Secondary storage. The number of clock cycles required for completion of execution of the sequence of instructions is ______. P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns. } SIMD represents an organization that _____. Assume that all the cache are direct mapped caches. If the target of the branch instruction is. The cache is initially empty and no pre-fetching is done. A machine has a 32-bit architecture, with 1-word long instructions. The main memory block numbered j must be mapped to any one of the cache lines from. Consider the following sequence of micro-operations. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. The PO stage takes 1 clock cycle for ADD or SUB instuction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. 1 Computer Architecture Computer Organization 1 1 Computer Design –4 Positional Numbering Systems 4 –8 Binary Data Representation 8 –12 12 Hamming Codes –15 Booth’s Algorithm 15 –25 CPU Design . This computer organization gate questions based tutorial provides some practice questions for GATE CS/IT Exam.Computer organization and architecture is an important subject for GATE CSE Exam. Let the addresses of two consecutive bytes in main memory be (E201F)16 and (E2020)16. /* Initialize array ARR to 0.0 * / III. BRANCH to Label if R1 == 0 Each instruction can have atmost two source operands and one destination operand.      Store in memory at address given by address register The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ____________.